1. Field of the Invention
The present invention generally relates to virtual storage mechanisms for data processing systems and, more particularly, to an efficient translation mechanism that eliminates multiple requests for the same page translation with multiple address generators.
2. Description of the Prior Art
Virtual storage organization and management for data processing systems are described, for example, by Harvey M. Deitel in An Introduction to Operating Systems, Addison-Wesley (1984), by Harold Lorin and Harvey M. Deitel in Operating Systems, Addison-Wesley (1981), and by Harold S. Stone in High- Performance Computer Architecture, Addison-Wesley (1987). In a virtual storage system, paging is a relocation and address-to-physical-location binding mechanism providing the user of the system with what appears to be a considerably larger memory space than is really available. The key feature of the virtual storage concept is disassociating the addresses referenced in a running process from the addresses available in main storage. The addresses referenced by the running process are called virtual addresses, while the addresses available in main storage are called real addresses. The virtual addresses must be mapped into real addresses as the process executes, and that is the function of the dynamic address translation (DAT) mechanism. One such mechanism employs a directory look aside table (DLAT), sometimes referred to as a translation look-aside buffer (TLB), which stores recent virtual address translations. For virtual addresses stored in the DLAT, the translation process requires only a single or, at most, a couple of machine cycles. For addresses not stored in the DLAT, the DAT process may take from fifteen to sixty cycles or more. The translation mechanism that performs the translation of addresses not stored in the DLAT is referred to as the buffer control element (BCE).
Translations from the virtual address to the real address must be made to find where the addressed instruction or data is in main memory. In typical applications, a processor generates only one address per cycle. Some processors have more than one address generator going to a DLAT (or TLB), but still only one address is actually translated per cycle. As processors have evolved, there has developed a need to generate and translate more than a single address per cycle. Specifically, the processor requires more than one memory request every cycle to be fully utilized. The requests may be, for example, three separate instructions so that three addresses must be generated every cycle to make the memory requests. The above-referenced U.S. Pat. No. 5,341,485 to Hattersley describes several address translation mechanisms which support multiple address generators.
When multiple address generators are running in parallel, either with their own DLAT mechanism or with a shared DLAT mechanism, there is the possibility that a request for the translation of the same page address will be made by a plurality of the address generators. If the translation is not already in the DLAT, then the translation requests are made to the BCE. Each of the translation requests to the BCE are queued, and the translations are each made thereby greatly increasing the translation times.